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cmos, 12 - bit, monolithic multiplying dac data sheet ad7541a rev. c docume nt feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from it s use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technolo gy way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2017 analog devices, inc. all rights reserved. technical support www.analog.com features improved v ersion of the obsoleted product, ad7541 full 4 q uadrant m ultiplication 12- b it l inearity ( e ndpoint) all parts guaranteed monotonic ttl/cmos c ompatible protection schottky diodes not required low logic input leakage applications waveform generators analog processing instrumentation applications programmable amplifiers and attenuators digitally controlled calibration programmable filters and oscillators composite video ultrasound gain, offset, and voltage trimming functional block dia gram digital inputs (dtl/ttl/cmos compatible) logic: a switch is closed to i out 1 for its digital input in a high state. 20k s1 10k 20k s2 10k 20k s3 10k 20k s12 20k v ref out 2 bit 1 (msb) out 1 bit 2 bit 3 bit 12 (lsb) r feedback 10k 00718-001 figure 1. general description the ad7541a is a high performance , 12- bit monolithic multiplying digital - to - analog converter (dac). it is fabricated using advanced , low noise, thin film, complementary metal - oxide semiconductor (cmos) technology . the ad7541a is available in 18- lead p dip , 1 8 - lead plcc, and 18 - lead soic packages . the ad7541a is functionally and pin compatible with the industry standard ad7541, and it offers improved specifications and performance over the obsolete product, ad7541. the improved design ensures that the ad7541a is latch - up free; therefore, no output protection schottky diodes are required. th e ad7541a uses laser wafer trimming to provide full 12- bit endpoint linearity with several high performance grades. product highlights compatibility t he ad7541a can be used as a di rect replacement for any ad7541 type device. as with the a d7541, t he digital inputs on the ad7541a are ttl/cmos compatible. they have a 1 a maximum input current requirement so that they do no t load the driving circuitry. improvements the ad7541a offers the following improved specifications over the ad7541: 1. gain error for all grades are reduced with premium grade versions having a maximum gain error of 3 lsb. 2. gain error temperature coe fficient are reduced to 2 ppm/c typical and 5 ppm/c maximum. 3. digital - to - analog charge injection energy for the ad7541a is typically 20% less than the standard ad7541. 4. latch - up proof. 5. l aser wa fer trimming provide s 1/2 lsb max imum differential nonlinearity for top grade devices over the operating temperature range (vs . 1 lsb on previous ad7541 devices ). 6. all grades are guaranteed monotonic to 12 bits over the operating temperature range.
ad7541a* product page quick links last content update: 03/20/2017 comparable parts view a parametric search of comparable parts. documentation application notes ? an-225: 12-bit voltage-output dacs for single-supply 5v and 12v systems data sheet ? ad7541a: cmos, 12-bit, monolithic multiplying dac ? ad7541a: military data sheet reference materials solutions bulletins & brochures ? digital to analog converters ics solutions bulletin design resources ? ad7541a material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7541a engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad7541a data sheet rev. c | page 2 of 13 tabl e of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac performance characteristics ................................................ 4 absolute maximum r atings ............................................................ 5 esd caution .................................................................................. 5 pin configurations ........................................................................... 6 terminology .......................................................................................7 theory of operation .........................................................................8 equivalent circuit analysis .........................................................8 applications infor mation .................................................................9 unipolar binary operation (two quadrant multiplication) ......9 bipolar operation (four quadrant multiplication) .............. 1 0 applications hints ...................................................................... 11 single - supply operation ........................................................... 11 supplemental application material ......................................... 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 13 revision history 3 / 2017 rev. b to rev. c updated format .................................................................. universal deleted e - 20a and q - 18 .............................................. throughout added applications section ............................................................ 1 changes to the general description section ................................ 1 changes to figure 7 .......................................................................... 9 changes to bipolar operation (four quadrant multiplication) section, figure 8 , and figure 9 ..................................................... 10 chang es to figure 10 ...................................................................... 11 changes to output offset section, temperature coefficient section, single - supply operation section, and supplemental application material section ........................................................ 11 update outline dimensions ......................................................... 13 changes to ordering guide .......................................................... 14
data sheet ad7541a rev. c | page 3 of 13 specifications v dd = 15 v , v ref = 10 v , out 1 = out 2 = gnd = 0 v , unless otherwise noted . temperature range is as follows for the j version and the k version : 0 c to +70 c . table 1 . parameter version t a = 25c t a = t min , t max unit test conditions/comments accuracy resolution all 12 12 bits relative accuracy j 1 1 lsb max 1 lsb = 0.024% of full scale k 1/2 1/2 lsb max 1/2 lsb = 0.012% of full scale differential nonlinearity j 1 1 lsb max all grades guaranteed monotoni c to 12 bits, t min to t max . k 1/2 1/2 lsb max gain error j 6 8 lsb max measured using internal r f eedback and includes effect of leakage current and gain temperature coefficient (tc); g ain error can be trimmed to zero k 3 5 lsb max gain tc 1 gain/temperature all 5 5 ppm/c max typical value is 2 ppm/c output leakage current out 1 (pin 1) j, k 5 10 na max all digital inputs = 0 v out 2 (pin 2) j, k 5 10 na max all digital inputs = v dd reference input input resistance (pin 17 to gnd) all 7 to 18 7 to 18 k? min/max typical input resistance = 11 k? ; t ypical input resistance tc = ?300 ppm/c digital inputs input voltage high , v ih all 2.4 2.4 v min low , v il all 0.8 0.8 v max in put current , i in all 1 1 a max logic inputs are mos gates ; i in typ ical (25c) = 1 na input capacitance , c in 1 all 8 8 pf max v in = 0 v power supply rejection gain/v dd all 0.01 0.0 2 % per % max v dd = 5% power supply v dd range all 5 to 16 5 to 16 v min/v max accuracy is not guaranteed over this range i dd all 2 2 ma max all digital inputs v il or v ih 100 500 a max all digital inputs 0 v or v dd 1 guaranteed by design but not production tested .
ad7541a data sheet rev. c | page 4 of 13 ac performance char acteristics these characteristics are included for design guidance only and are not subject to test. v dd = 1 5 v, v in = 1 0 v, and out 1 = out 2 = gnd = 0 v, unless otherwise noted . temperature range is as follows for the j version and the k version : 0 c to +70 c . table 2 . parameter t a = 25c t a = t min ,t max unit test conditions/comments propagation delay (from digital input change to 90% of final analog output) 100 ns typ out 1 l oad = 100 ? , c ext = 13 pf ; d igital i nputs = 0 v to v dd or v dd to 0 v digital - to - analog glitch impulse 1000 nv -s ec typ v ref = 0 v; all digital inputs 0 v to v dd or v dd to 0 v; measured using model 50k as output amplifier multiplying feedthrough error (v ref to out 1) 1.0 mv p -p typ v ref = 10 v, 10 khz sine wave output current settling time 0.6 s typ to 0.01% of full - scale range; out 1 load = 100 ?, c ext = 13 pf; d igital inputs = 0 v to v dd or v dd to 0 v output capacitance c out 1 (pin 1) 2 00 2 00 pf max digital i nputs = v ih 70 70 pf max digital i nputs = v il c out 2 (pin 2) 70 70 pf max digital i nputs = v ih 200 200 pf max digital i nputs = v il
data sheet ad7541a rev. c | page 5 of 13 absolute maximum rat ings t a = 25 c , unless otherwise noted . table 3 . parameter rating v dd to gnd 17 v v ref to gnd 25 v v r f eedback to gnd 25 v digital input voltage to gnd ? 0.3 v, v dd + 0.3 v out 1, o ut 2 to gnd ? 0.3 v, v dd + 0.3 v power dissipation (any package) to 75 c 450 mw derates a bove 75 c 6 mw/ c operating temperature range commercial (j version / k version ) 0 c to 70 c storage temperature ? 65 c to +150 c lead temperature (soldering, 10 secs) 300 c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the opera tional section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caution
ad7541a data sheet rev. c | page 6 of 13 pin configuration s ad7541a top view (not to scale) out 1 1 r feedback 18 out 2 2 v ref in 17 gnd 3 v dd (+) 16 bit 1 (msb) 4 bit 12 (lsb) 15 bit 2 5 bit 11 14 bit 3 6 bit 10 13 bit 4 7 bit 8 12 bit 5 8 bit 8 11 bit 6 9 bit 7 10 00718-002 figure 2. 18 - lead pdip and 18 - lead soic pin configuration 4 gnd 5 bit 1 (msb) 6 bit 2 7 bit 3 8 bit 4 18 v dd 17 bit 12 (lsb) 16 bit 11 15 bit 10 14 bit 9 19 v ref 20 r feedback 1 nc 2 out 1 3 out 2 13 bit 8 12 bit 7 11 nc 10 bit 6 9 bit 5 ad7541a top view (not to scale) notes 1. nc = no connect. 00718-003 figure 3. 20 - lead plcc pin configuration
data sheet ad7541a rev. c | page 7 of 13 terminology relative accuracy relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the end points of the dac transfer function. it is measured after adjusting for zero scale and full scale , and it is expressed in % of full - scale range or (sub) multiples of 1 lsb. differential nonlinearity differential nonli nearity is the difference between the m easured change and the ideal l lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb max imum over the operating temperature range e nsures monotonicity. gain error gain error is a measure of the output error between an i deal dac and the actual device output. for the ad7541a , ideal maximum output is ?(4095/40 96)( v ref ) gain error is adjustable to zero using external trims, as shown in figure 7 , figure 8 , and figure 9 . output leakag e current current that appears at out i with the dac loaded to all 0s or at out 2 with the dac loaded to all 1s. multiplying feedthrough error ac error due to capacitive feedthrough from the v ref terminal to out 1 with the dac loaded to all 0s. output curr ent settling time time required for the output function of the dac to settle to within 1/2 lsb for a given digital input stimulus, that is , 0 to full scale. propagation delay th e propagation delay is a measure of the internal delay of the circuit , and it i s measured from the time a digital input changes to the point at which the analog output at out 1 reaches 90% of its final value. digital -to - analog glitch impulse (qda) th e qda is a measure of the amount of charge injected from the digital inputs to the an alog outputs when the inputs change state. it is usually specified as the area of the glitch in nv - sec and is measured with v ref = gnd and a model 50k as the output op amp, c1 (phase compensation) = 0 pf.
ad7541a data sheet rev. c | page 8 of 13 theory of operation the simplified digital - to - a nalog circuit is shown in figure 4 . an inverted r - 2r ladder structure wa s used , meani ng the binarily weighted currents are switched between the out 1 and out 2 bus lines, thus maintaining a constant current in each ladder leg indep endent of the switch state. digital inputs (dtl/ttl/cmos compatible) logic: a switch is closed to i out 1 for its digital input in a high state. 20k s1 10k 20k s2 10k 20k s3 10k 20k s12 20k v ref out 2 bit 1 (msb) out 1 bit 2 bit 3 bit 12 (lsb) r feedback 10k 00718-005 figure 4 . functional diagram (inputs h igh ) the input resistance at v re f ( see figure 4 ) i s always equal to r ldr , which is the r - 2r ladder characteristic resista nce and is equal to value r . because r in at the v ref pin is constant, the reference terminal can be driven by a reference voltage or a reference current, ac or dc, of positive or negative polarity. if a current source is used, a low temperature coefficient external r f eed b ack is reco mmended to define the scale factor. equivalent circuit a nalysis the equivalent circuits for all digital inputs low and all digital inputs high are shown in figure 5 and figur e 6 . in figure 5 with all digital inputs low , the reference current is switched to out 2. the current source , i leakage , is composed of surface and junction leakages to the substrate, while the i/ 4096 current source represents a co nstant 1 - bit current drain through the termination resistor on the r - 2r ladder. the on capacitance of the output n - channel switch is 200 pf, as shown on the out 2 terminal. the off switch capacitance is 70 pf, as shown on the out 1 terminal. analysis of th e circuit for all digital inputs high , as shown in figure 5 , is similar to figure 4 ; however, the on switches are now on the out 1 terminal ; therefore, 200 pf at that terminal. r feedback r 70pf out 1 i leakage 200pf out 2 i leakage i /4096 r 15k v ref i ref 00718-006 figure 5 . dac equivalent circuit, all digital inputs l ow r feedback r out 1 70pf i leakage out 2 200pf i leakage i /4096 r 15k v ref i ref 00718-007 figure 6 . dac equivalent circuit all digital inputs h igh
data sheet ad7541a rev. c | page 9 of 13 applications information unipolar binary oper ation ( two quadrant multiplication) figure 7 shows the analog circuit connections required for unipolar binary ( two quadrant multiplication) operation. with a dc reference voltage or current (positive or negative polarity) applied at pin 17, the circuit is a unipolar dac . with an ac reference volt age or current, the circuit provides two quadrant multiplication (digitally controlled attenuation). the input/output relationship is shown in table 5 . 1 2 17 out 1 out 2 2 gnd 18 r feedback v dd 16 v dd v ref in digital ground analog common ad7541a v in r1 1 v out c1 33pf r2 1 1 refer to table 4 pin 4 to pin 15 4 15 bit 1 to bit 12 00718-008 figure 7 . unipolar binary operation r1 provides ful l- scale trim capability ( that is , load the dac register to 1111 1111 1111, adjust r1 for v out = C v ref (4095/4096) ) . alternatively, f ull s cale can be adjusted by omitting r1 and r2 and trimming the reference voltage magnitude. c1 phase compensation (10 pf to 25 pf) may be required for stability when using high speed amplifiers. c1 is used to cancel the pole formed by the dac internal feedback resistance and output capacitance at out 1. amplifier a1 must be selected or trimmed to provide v os 10% of the voltage resolution at v out . additionally, the amplifier must exhibit a bias current that is low over the temperature range of interest (bias current causes output offset at v out equal to i b times the dac feedback resistance, nominally 11 k?). table 4 . recommended trim resistor values vs. grades trim resistor jn kn r1 100 ? 100 ? r2 47 ? 33 ? table 5 . unipolar binary code table for circuit of figure 7 binary numb er in dac msb lsb analog output, v out 1 1 1 1 1 1 1 1 ?v in (4095/4096) 1 0 0 0 0 0 0 0 0 0 0 0 ?v in (2048/4096) = ?1/2v in 0 0 0 0 0 0 0 0 0 0 0 1 ?v in (1/4096) 0 0 0 0 0 0 0 0 0 0 0 0 0 v
ad7541a data sheet rev. c | page 10 of 13 bipolar operation ( f our qua drant multiplication) figure 8 and table 6 illustrate the circuitry and code relationship for bipolar operation. with a dc reference (positive or negative polarity) , the circ uit provides offset binary operation. with an ac reference, the circuit provides full four quadrant multiplication. with the dac loaded to 1000 0000 0000, adjust r1 for v out = 0 v (alternatively, omit r1 and r2 and adjust the ratio of r3 to r4 for v out = 0 v). to accomplish, f ull - scale trimming , adjust the amplitude of v ref or vary the r5 value. as in unipolar operation, a1 must be chosen for low v os and low i b . r3, r4, and r5 must be selected for matc hing and tracking. mismatch of r3 to r4 causes both offs et and full - scale error. mismatch of r5 to r4 or r3 causes full - scale error. c1 phase compensation (10 pf to 50 pf) may be required for stability, depending on amplifier used. table 6 . bipolar code table for offset binary circuit of figure 8 binary number in dac msb lsb analog output, v out 1 1 1 1 1 1 1 1 1 1 1 1 + v in ( 2047 / 2048 ) 1 0 0 0 0 0 0 0 0 0 0 1 + v in ( 1 / 2048 ) 1 0 0 0 0 0 0 0 0 0 0 0 0 v 0 1 1 1 1 1 1 1 1 1 1 1 ? v in ( 1 / 2048 ) 0 0 0 0 0 0 0 0 0 0 0 0 ? v in ( 2048 / 2048 ) figure 9 and table 7 show an alternative method of achieving bipolar output. the circuit operates with sign plus magnitude code and has the advantage of gi ving 12 - bit resolution in each quadran t, compared with 11 - bit resolution per quadrant for the circuit of figure 8 . the adg5436f is a dual spdt, latch - u p immune switch. r4 a nd r5 must match each other to 0.01% to maintain the accuracy of the da c . mismatch between r4 and r5 introduces a gain error. table 7 . 12 - bit plus sign magnitude code table for circuit of figure 9 binary number in dac sign bit 1 msb lsb analog output, v out 0 1 1 1 1 1 1 1 1 1 1 1 1 + v in ( 4095/ 4096 ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 v 1 0 0 0 0 0 0 0 0 0 0 0 0 0 v 1 1 1 1 1 1 1 1 1 1 1 1 1 ? v in ( 4095/ 4096 ) 1 w hen the s ign bit equals 0 , it connects r3 to gnd. 1 2 17 out 1 out 2 2 dgnd 18 r feedback v dd 16 v dd v ref digital ground analog common a1 ad7541a v in r1 1 v out a2 c1 33pf r2 1 r3 10k r5 20k r6 5k 10% 1 for values of r1 and r2, see table 4. r4 20k pin 4 to pin 15 4 15 bit 1 to bit 12 00718-009 figure 8. bipolar operation ( four - quadrant multiplication) 1 2 17 out 1 out 2 2 dgnd 18 r feedback v dd 16 v dd v ref bit 1 to bit 12 digital ground analog common a1 ad7541a v in r1 1 c1 33pf r2 1 1 for values of r1 and r2, see table 4. v out a2 1/2 adg5436f r4 20k r3 10k 10% r5 20k pin 4 to pin 15 4 15 00718-010 figure 9 . 12 - bit plus sign magnitude operation
data sheet ad7541a rev. c | page 11 of 13 applica tions hints output offset the cm os da c s exhibit a code dependent , output resistance that can cause a code dependent error voltage at the output of the amplifier . the maximum amplitude of this offset, which adds to the nonlinearity of the da c , is 0.67 v os , where v os is the amplifier input offset voltage. to maintain monotonic operation , it is recommended that v os be no greater than (25 10 C 6 ) v ref over the temperature range of operation. suitable op amps include the follow ing: op27 , op177 , and op777 . the op27 is best s uited for fixed reference applications with low bandwidth requirements . the op27 has extremely low offset ( 25 v) , and does not require an offset trim in most applications. the ad711 has a much wider bandwidth and higher slew rate and is recommended for multiplying and other applications that require fast settling. digital glitches one cause of digital glitches is capacitive coupling fro m the digital lines to the out 1 and out 2 terminals . this coupling can be minimized by screening the analog pins of the ad7541a (pin 1, pin 2, pin 17, and pin 18) from the digital pins by a gr ound tra ck run between pin 2 and pin 3 and between pin 16 and pin 17 of the ad7541a . note how the analog pins are at one end of the package and are separated from the digital pins by v dd and gn d to aid screening at the board level. on - chip capacitive coupling can also give rise to crosstalk from the digital to analog sections of the ad7541a , particularly in circuits with high current s and fast rise and fall times. temperature coefficients the gain temperature coefficient of the ad7541a has a maximum value of 5 ppm/c and a typical value of 2 ppm/c. this coefficient corres ponds to worst case gain shifts of 2 lsb and 0.8 lsb, respectively, over a 100c temperature range. when trim resistors , r1 and r2 , are used to adjust the full - scale range, the temperature coefficient s of r1 and r2 must also be taken into account. si ngle - supply operation figure 10 shows the ad7541a connected in a voltage switching mode. out 1 is connected to the reference voltage , and out 2 is conne cted to gnd. the output voltage of the da c is available at the v ref pin (pin 17) and has a constant output impedance equal to r ldr . the feedback resistor , r f eed b ack , is not used in this circuit. v out v ref d (1 + r2/r1) where 0 d 1, that is, d is a fractional representation of the digital input 17 1 2 out 1 out 2 2 gnd r feedback 18 not used v dd 16 v ref pin 4 to pin 15 4 15 bit 1 to bit 12 v+ v? ad7541a v dd = 15v v out = 0v to 10v system ground v ref 2.5v r2 30k r1 10k 00718-0 1 1 figure 10 . single supply operation using voltage switching mode the reference voltage must always be positive. if out 1 goes more than 0.3 v less than gnd, an internal diode is turned on and a heavy current may flow , causing device damage (the ad7541a is protected from the scr latch - up phenomenon prevalen t in many cmos devices). suitable references include the adr431 , the adr441 , a nd the ref192 . the loading on the reference voltage source is code dependent , and the behavior of the reference voltage with changing load conditions often determines th e response time of th e circuit . to maintain linearity, the voltage at out 1 must remain within 2.5 v of gnd for a v dd of 15 v. if v dd is reduced from 15 v , or if the reference voltage at out 1 is increased to more than 2.5 v, the differential nonlinearity of the dac increase s, and the linearity of the dac degrade s. supplemental applica tion material for further information on cmos multiplying d ac s, refer to the following: analog - digital conversion handbook, 1972 , analog devices, inc. cmos dac application g uide, 1984 , analog devices analog - digital conversion handbook, 1986 , analog devices
ad7541a data sheet rev. c | page 12 of 13 outline dimensions compliant to jedec standards mo-047-aa controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.020 (0.50) r bottom view (pins up) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.290 (7.37) 0.032 (0.81) 0.026 (0.66) 0.056 (1.42) 0.042 (1.07) 0.20 (0.51) min 0.120 (3.04) 0.090 (2.29) 3 4 19 18 8 9 14 13 top view (pins down) 0.395 (10.03) 0.385 (9.78) sq 0.356 (9.04) 0.350 (8.89) sq 0.048 (1.22 ) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.020 (0.51) r 0.050 (1.27) bsc 0.180 (4.57) 0.165 (4.19) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier figure 11 . 20 - lead plastic leadless chip carrier [plcc] (p- 20) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in p arentheses) are rounded-off inch equi v alents for reference on l y and are not appropri a te for use in design. corner leads m a y be configured as whole or half leads. compliant t o jedec s t andards ms-001 070706- a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0. 1 15 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 18 1 9 10 0.100 (2.54) bsc 0.920 (23.37) 0.900 (22.86) 0.880 (22.35) 0.210 (5.33) max sea ting plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7. 1 1) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0. 1 15 (2.92) figure 12 . 18 - lead plastic dual in - line package [pdip] (n - 18) dimensions shown in inches and (millimeters)
data sheet ad7541a rev. c | page 13 of 13 controlling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equi v alents for reference on l y and are not appropri a te for use in design. compliant t o jedec s t andards ms-013-ab 0.30 (0.0 1 18) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) coplanarit y 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) se a ting plane 8 0 18 10 9 1 1.27 (0.0500) bsc 1 1.75 (0.4626) 1 1.35 (0.4469) 060706- a 45 figure 13 . 18 - lead standard small outline package [ soic _w ] (r w - 18) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range relative accuracy , t min to t max error , t a = 25c package description package option ad7541ajn z 0c to +70c 1 lsb 6 lsb 18- lead pdip n -18 ad7541akn z 0c to +70c 1/2 lsb 3 lsb 18- lead pdip n -18 ad7541ajp z - reel 0c to +70c 1 lsb 6 lsb 20- lead plcc p -20 ad7541akp z - reel 0c to +70c 1/2 lsb 3 lsb 20- lead plcc p -20 ad7541akr 0c to +70c 1/2 lsb 3 lsb 18- lead soic_w rw - 18 ad7541akrz 0c to +70c 1/2 lsb 3 lsb 18- lead soic_w rw - 18 ad7541akr z - reel 0c to +70c 1/2 lsb 3 lsb 18- lead soic_w rw - 18 ad7541akr z C reel7 0c to +70c 1/2 lsb 3 lsb 18- lead soic_w rw - 18 ad7541aachips d ie 1 z = rohs compliant part. ? 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00718 - 0 - 3/17(c)

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